1. Field of the Invention
The present invention relates to decoding methods and decoding devices for variable length decoding and run length decoding coded data coded using variable length coding and run length coding. In particular, the present invention relates to variable length decoding methods and variable length decoding devices used in image decompression technique of decompressing the compressed image data. The present invention also relates to image capturing system.
2. Description of the Related Art
The compression/decompression method using run length codes and variable length codes is used in JPEG (Joint Photographic Experts Group) and MPEG (Moving Picture Experts Group), which are general compression techniques of image data, and is widely used as a technique that allows data transfer with a small amount of information through widespread use of digital cameras and digital video cameras as well as development in communications technique.
The configuration of a typical image compression device is shown in FIG. 31, and the following description will be made with reference to FIG. 31. Image data is sequentially input after being divided to blocks each having eight by eight pixels in advance. A DCT (Discrete Cosine Transform) unit 101 generates DCT coefficients by frequency transforming the image data with discrete cosine transformation. Since the change in color is usually smooth in a natural image, DCT coefficients of a large value are distributed in a low frequency region m and DCT coefficients of a small value are distributed in a high frequency region n when DCT coefficients are generated through frequency transformation, as shown in FIG. 32. In particular, the coefficient o on the upper left corner is referred to as the DC component that does not have frequency component, and other coefficients are referred to as AC components.
A quantization unit 102 divides a DCT coefficient with a quantization value set in advance to generate a quantization coefficient. According to such process, a coefficient of “0” (zero coefficient) can be concentrated at the high frequency region that does not influence the image quality.
Furthermore, run length data is sequentially generated in a variable length coding unit 103 by combining RUN representing the number of “0” and LEVEL representing the size of a coefficient value in the order of zigzag scan, as shown in FIG. 33. A code word having a different length is then allocated according to the appearance ratio of such combination to reduce the volume of the data.
On the other hand, the image decompression device for decoding the variable length coded data coded by the above configuration includes a variable length decoding unit 104, an inverse quantization unit 105, and an inverse DCT unit 106 corresponding to the image compression device, as shown in FIG. 34.
The variable length decoding unit 104 decodes the variable length coded data as a combination of the RUN representing the number of “0” and the LEVEL representing the size of a coefficient value, generates zero coefficients by the size of the RUN, and combines the generated zero coefficients and the coefficients represented by the LEVEL. This operation is repeated until coefficients are generated for eight by eight pixels. The inverse quantization unit 105 multiples a quantization value set in advance and the generated coefficients for eight by eight pixels together to generate an inverse quantization DCT coefficient. The inverse DCT unit 106 converts the generated inverse quantization DCT coefficients in a frequency region to those in a spatial region to decode as image data.
The configuration of the conventional variable length decoding unit 104 will now be described with reference to FIG. 35. A variable length decoder 108 decodes variable length coded data input from an input section 107 as a combination of the RUN representing the number of “0” and the LEVEL representing the size of a coefficient value. A write controller 109 provides a selection signal to a selector 110 in order for the selector 110 to write “0” to a data buffer 112 by the number of decoded RUN. The selector 110 then writes to the data buffer 112 “0” by the number of RUN. After writing “0”, the selector 110 writes coefficients represented by the LEVEL to the data buffer 112. After such operation is repeated for eight by eight pixels, a read controller 111 sequentially reads the data from the data buffer 112 through zigzag scan (FIG. 33), and outputs the read data from an output section 113 to the inverse quantization unit 105.
However, in the conventional configuration, a wasteful time is produced during the period the coefficient or “0” is successively written by the number of RUN because the variable decoder 108 cannot perform any process, which inhibits speed up of the decoding processing.
One solution to such drawback is a decoding circuit of run length codes. One example of its configuration will be described with reference to FIG. 36. In FIG. 36, reference numeral 202 is an input section which inputs variable length coded/run length coded data. Numeral 203 is a variable length decoder which sequentially decodes the data input from the input section 202 as a combination of the RUN representing the number of “0” and the LEVEL representing the size of a coefficient value. Numeral 204 is a data buffer which stores the LEVEL. Numeral 205 is an address adder which computes the address of the LEVEL corresponding to this data based on the number of “0” by RUN. Numeral 206 is an information register of M×N bits which stores the result of the address adder 205. Numeral 207 is a write controller which stores the LEVEL to the data buffer 204 based on the information from the address adder 205. Numeral 208 is a read controller which reads the LEVEL from the data buffer 204 based on the value of the information register 206. Numeral 209 is a selector which selects and outputs either the LEVEL stored in the data buffer 204 or “0” based on the value of the information register 206. Numeral 210 is a post-stage processor which performs post-stage processing on the data from the selector 209. Numeral 211 is an output section which outputs the data from the post-stage processor 210.
When variable length coded/run length coded data is input from the input section 202, the variable length decoder 203 sequentially decodes the input variable length coded/run length coded data as a combination of the RUN representing the number of “0” and the LEVEL representing the size of a coefficient value.
The address adder 205 computes the address based on the size of the decoded RUN in the order of zigzag scan shown in FIG. 33, that is, 1→2→9→17 . . . in the decoded data. The information register 206 successively stores “0” for example, by the size of the RUN in the order of zigzag scan, and stores “1” for example as the address of the LEVEL in the subsequent position. The write controller 207 writes the LEVEL to the address computed by the address adder 205.
The write controller 207 determines whether or not the writing of the LEVEL for one block is terminated, and the process returns to the first step of decoding if determined as not terminated, and the process proceeds to the reading process when determined as terminated. After the combination of the RUN and the LEVEL equivalent to one block is decoded by the variable length decoder 203 and writing of the LEVEL is terminated, the read controller 208 determines the stored content of the information register 206 based on the control signal indicating the permission for reading from the post-stage processor 210, and controls the reading process based on the determination result. That is, the read controller 208 outputs the address equivalent to the bit having “1” stored in the information register 206 to the data buffer 204, and reads the LEVEL stored in the relevant address. In the selector 209, when the determination of the information register 206 is made by the read controller 208, and at the same time, when the bit of the information register 206 is “0”, “0” is output to the post-stage processor 210, and the output data LEVEL read from the data buffer 204 is output to the post-stage processor 210 when the bit is “1”. The post-stage processor 210 performs post-stage processing on the data received via the selector 209, and outputs the processed data from the output section 211.
According to the prior art, the selector 209 is arranged at the post-stage of the data buffer 204, and only the LEVEL is stored in the data buffer 204 and “0” is not stored therein. Therefore, “0” is selected in the post-stage selector 209. The variable length decoder 203 does not need to stop its operation, which is advantageous in increasing the speed. Furthermore, the variable length decoder of low power consumption can be obtained in a minimum required configuration since the access to the data buffer 204 can be reduced by reading out only the LEVEL based on the information of the holder of the address.
On the other hand, presently, H264 coding method (hereinafter referred to as H.264) is given attention as a compression technique following MPEG 4. FIG. 37 is a typical processing block of H.264, which is configured by four by four pixels. The features of the variable length coding of H.264 lie in that TotalCoeff representing the number of non-zero coefficients in the block, LEVEL representing the size of a non-zero coefficient value, total_zeros representing the number of zero coefficients before the last LEVEL in the data scanning direction, and run_before representing the number of successive zero coefficients before the LEVEL in the data scanning direction are coded, and RUN and LEVEL are not coded as a combination, as opposed to JPEG, MPEG 2, and MPEG 4. H.264 is explained in detail in Impress Co. standard textbook “H.264/AVC textbook”.
The information cannot be stored in a information register with the conventional configuration that assumes that the combination of RUN and LEVEL is being decoded since the combination of RUN and LEVEL is not decoded in H.264.